Prindle, C. - motorola | 人才画像

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EUVパターン形成と二重歪高移動度チャンネルを特徴とする7nm FinFET技術【Powered by NICT】

R Xie,P Montanini,K Akarvardar,N Tripathi,B Haran, S Johnson,T Hook,B Hamieh,D Corliss, J Wang,X Miao, J Sporre,J Fronheiser,N Loubet,M Sung,S Sieg,S Mochizuki,C Prindle,S Seo,A Greene,J Shearer,A Labonte,S Fan,L Liebmann,R Chao,A Arceo,K Chung,K Cheon,P Adusumilli,H P Amanapu,Z Bi,J Cha, Chen H.-C.,R Conti,R Galatage,O Gluschenkov,V Kamineni, K Kim, C Lee,F Lie, Z Liu,S Mehta, Elias Miller,H Niimi,C Niu, C Park,D Park,M Raymond,B Sahu,M Sankarapandian,S Siddiqui,R Southwick, L Sun,C Surisetty,S Tsai,S Whang, Peijie Xu, Yuxuan Xu,C Yeh,P Zeitzoff, J Zhang, J Li,J Demarest,J Arnold,D Canaperi,D Dunn,N Felix,D Gupta,H Jagannathan,S Kanakasabapathy,W Kleemeier,C Labelle,M Mottura,P Oldiges,S Skordas,T Standaert, T Yamashita,M Colburn,M Na,V Paruchuri,S Lian,R Divakaruni, T Gow, S Lee,A Knorr,H Bu,M Khare

IEEE Conference Proceedings (2016): 4

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A 7nm Finfet Technology Featuring Euv Patterning and Dual Strained High Mobility Channels

R. Xie,P. Montanini,K. Akarvardar,N. Tripathi,B. Haran, S. Johnson,T. Hook,B. Hamieh,D. Corliss,J. Wang,X. Miao, J. Sporre,J. Fronheiser,N. Loubet,M. Sung,S. Sieg,S. Mochizuki,C. Prindle,S. Seo,A. Greene,J. Shearer,A. Labonte,S. Fan,L. Liebmann,R. Chao,A. Arceo,K. Chung,K. Cheon,P. Adusumilli,H. P. Amanapu,Z. Bi,J. Cha,H. -C. Chen,R. Conti,R. Galatage,O. Gluschenkov,V. Kamineni,K. Kim,C. Lee,F. Lie,Z. Liu,S. Mehta,E. Miller,H. Niimi,C. Niu,C. Park,D. Park,M. Raymond,B. Sahu,M. Sankarapandian,S. Siddiqui,R. Southwick,L. Sun,C. Surisetty,S. Tsai,S. Whang,P. Xu,Y. Xu,C. Yeh,P. Zeitzoff,J. Zhang,J. Li,J. Demarest,J. Arnold,D. Canaperi,D. Dunn,N. Felix,D. Gupta,H. Jagannathan,S. Kanakasabapathy,W. Kleemeier,C. Labelle,M. Mottura,P. Oldiges,S. Skordas,T. Standaert,T. Yamashita,M. Colburn,M. Na,V. Paruchuri,S. Lian,R. Divakaruni, T. Gow,S. Lee,A. Knorr,H. Bu,M. Khare

2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2016）

引用154浏览0EIWOS引用

154

A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI

K. -I. Seo,B. Haran,D. Gupta,D. Guo,T. Standaert,R. Xie,H. Shang,E. Alptekin, D. -I. Bae,G. Bae,C. Boye,H. Cai,D. Chanemougame,R. Chao,K. Cheng,J. Cho,K. Choi,B. Hamieh,J. G. Hong,T. Hook, L. Jang, J. Jung, R. Jung,D. Lee,B. Lherron,R. Kambhampati,B. Kim,H. Kim,K. Kim,T. S. Kim,S. -B. Ko,F. L. Lie,D. Liu,H. Mallela,E. Mclellan,S. Mehta,P. Montanini,M. Mottura, J. Nam,S. Nam, F. Nelson,I. Ok,C. Park,Y. Park,A. Paul,C. Prindle,R. Ramachandran,M. Sankarapandian,V. Sardesai,A. Scholze,S. -C Seo,J. Shearer,R. Southwick,R. Sreenivasan, S. Stieg,J. Strane,X. Sun,M. G. Sung,C. Surisetty,G. Tsutsui,N. Tripathi,R. Vega,C. Waskiewicz,M. Weybright,C. -C. Yeh,H. Bu,S. Burns,D. Canaperi,M. Celik,M. Colburn,H. Jagannathan, S. Kanakasabaphthy,W. Kleemeier,L. Liebmann,D. Mcherron,P. Oldiges,V. Paruchuri,T. Spooner,J. Stathis,R. Divakaruni, T. Gow,J. Iacoponi, J. Jenq,R. Sampson,M. Khare

Symposium on VLSI Technology（2014）

引用99浏览0EIWOS引用

10Nm FINFET Technology for Low Power and High Performance Applications

D. Guo,H. Shang,K. Seo,B. Haran,T. Standaert,D. Gupta,E. Alptekin,D. Bae,G. Bae,D. Chanemougame,K. Cheng,J. Cho,B. Hamieh,J. Hong,T. Hook, J. Jung,R. Kambhampati,B. Kim,H. Kim,K. Kim,T. Kim,D. Liu,H. Mallela,P. Montanini,M. Mottura,S. Nam, L. Ok,Y. Park,A. Paul,C. Prindle,R. Ramachandran,V. Sardesai,A. Scholze,S. Seo,R. Southwick,J. Strane,X. Sun,G. Tsutsui,N. Tripathi,R. Vega,M. Weybright,R. Xie,C. Yeh,H. Bu,S. Burns,D. Canaperi,M. Celik,M. Colburn,H. Jagannathan, S. Kanakasabaphthy,W. Kleemeier,L. Liebmann,D. Mcherron,P. Oldiges,V. Paruchuri,T. Spooner,J. Stathis,R. Divakaruni, T. Gow, J. Jacoponi, J. Jenq,R. Sampson, W. Yang,M. Khare

2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) (2014)

引用8浏览0EIWOS引用

SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT PLUGS, AND RELATED FABRICATION METHODS

C Prindle, Richard J Carter, Doug Lee,M F Ng

mag（2010）

引用30浏览0引用

High Performance 45-Nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

S. Narasimha,K. Onishi,H. M. Nayfeh,A. Waite,M. Weybright, J. Johnson,C. Fonseca,D. Corliss, C. Robinson,M. Crouse, D. Yang, C-H. J. Wu,A. Gabor,T. Adam,I. Ahsan,M. Belyansky,L. Black, S. Butt,J. Cheng,A. Chou,G. Costrini,C. Dimitrakopoulos,A. Domenicucci,P. Fisher, A. Frye,S. Gates,S. Greco,S. Grunow,M. Hargrove,J. Holt,S-J. Jeng, M. Kelling,B. Kim,W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu,N. Lustig, A. McKnight, L. Nicholson,D. Nielsen,K. Nummy,V. Ontalus,C. Ouyang,X. Ouyang,C. Prindle,R. Pal,W. Rausch,D. Restaino,C. Sheraw,J. Sim, A. Simon,T. Standaert,C. Y. Sung,K. Tabakman,C. Tian, R. Van Den Nieuwenhuizen,H. Van Meer,A. Vayshenker,D. Wehella-Gamage,J. Werking, R. C. Wong, J. Yu,S. Wu,R. Augur, D. Brown, X. Chen,D. Edelstein,A. Grill,M. Khare, Y. Li,S. Luning,J. Norum,S. Sankaran,D. Schepis,R. Wachnik,R. Wise,C. Wann,T. Ivers,P. Agnello

2006 International Electron Devices Meeting（2006）

引用114浏览0EIWOS引用

114

General Review of Issues and Perspectives for Advanced Copper Interconnections Using Air Gap As Ultra-Low K Material

LG Gosset,V Arnal,C Prindle,R Hoofman,G Verheijden,R Daamen,L Broussous,F Fusalba,M Assous, R Chatterjee,J Torres,D Gravesteijn,KC Yu

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat No03TH8695)

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Method for depositing barrier layers in an opening

Dean J Denning,Da Zhang,C Prindle,I Shahvandi

mag（2003）

引用23浏览0引用

TiZrN as a copper barrier for 0.13 mu m and 0.09 mu m technology nodes

D Denning, L Svedberg,C Prindle

ELECTROCHEMICAL SOCIETY SERIESno. 13.0 (2003): 147-153

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