Dave Bradley

Dave Bradley (M’15) received the B.S.E.E. degree in 1996 from Virginia Tech, Blacksburg, VA, USA. He has since been a VLSI designer for HP and now Intel. He has served as a lead physical designer on L1 and L2 caches on previous Itanium processors, and he has more recently served as a Principal Engineer at Intel leading the high-speed serial I/O designs for the Tukwila (65 nm) Itanium processor and the Haswell (22 nm) Xeon® processor family. His current professional interests are largely focused around high speed serial I/O design as well as defining robust analog design methodologies for server processors.