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Research Interests

Papers共 9 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选
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Intel 4 CMOS Technology Featuring Advanced FinFET Transistors Optimized for High Density and High-Performance Computing
B. Sell, S. An, J. Armstrong, D. Bahr, B. Bains, R. Bambery, K. Bang,D. Basu, S. Bendapudi,D. Bergstrom, R. Bhandavat, S. Bhowmick,M. Buehler, D. Caselli, S. Cekli, Vrsk. Chaganti, Y. J. Chang,K. Chikkadi,T. Chu, T. Crimmins, G. Darby,C. Ege, P. Elfick, T. Elko-Hansen,S. Fang, C. Gaddam,M. Ghoneim,H. Gomez,S. Govindaraju, Z. Guo,Walid M. Hafez,M. Haran,M. Hattendorf, S. Hu,A. Jain,S. Jaloviar,M. Jang, J. Kameswaran, V. Kapinus, A. Kennedy,S. Klopcic, D. Krishnan,J. Leib, Y.-T. Lin,N. Lindert,G. Liu, O. Loh,Y. Luo, S. Mani, M. Mleczko, S. Mocherla,P. Packan, M. Paik, A. Paliwal, R. Pandey, K. Patankar,L. Pipes,P. Plekhanov,Chetan Prasad,M. Prince, G. Ramalingam,R. Ramaswamy, J. Riley, J. R. Sanchez Perez,J. Sandford,A. Sathe, F. Shah, H. Shim,S. Subramanian, S. Tandon, M. Tanniru, D. Thakurta,T. Troeger,X. Wang, C. Ward, A. Welsh, S. Wickramaratne, J. Wnuk, S. Q. Xu,P. Yashar, J. Yaung, K. Yoon, N. Young
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）
Cited22Views0EIWOSBibtex
22
0
活性ゲートとコバルト局所相互接続上の接触10nm高性能および低電力CMOS技術を特徴とする3~rd発生FinFETトランジスタ,自己整合4パターン形成【Powered by NICT】
C Auth, A Aliyarukunju,M Asoro,D Bergstrom,V Bhagwat, J Birdsall, N Bisnik,M Buehler,V Chikarmane, G Ding, Q Fu,H Gomez,W Han, D Hanken,M Haran,M Hattendorf,R Heussner,H Hiramatsu, B Ho,S Jaloviar,I Jin,S Joshi, S Kirby, S Kosaraju,H Kothari,G Leatherman, K Lee,J Leib,A Madhavan, K Marla, H Meyer,T Mule,C Parker, S Parthasarathy,C Pelto,L Pipes,I Post,M Prince,A Rahman, S Rajamani, A Saha, Santos J. Dacuna,M Sharma, Vrinda Sharma,J Shin,P Sinha, P Smith,M Sprinkle, A Amour, C Staus, R Suri, D Towner, Aditi Kumar Tripathi,A Tura, C Ward,A Yeoh
IEEE Conference Proceedings (2017): 1-29
Cited0Views0Bibtex
0
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A 14nm Logic Technology Featuring 2Nd-Generation FinFET, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588 Μm2 SRAM Cell Size
S. Natarajan,M. Agostinelli, S. Akbar,M. Bost,A. Bowonder,V. Chikarmane,S. Chouksey, A. Dasgupta, K. Fischer, Q. Fu,T. Ghani, M. Giles,S. Govindaraju, R. Grover, W. Han, D. Hanken, E. Haralson, M. Haran, M. Heckscher,R. Heussner, P. Jain, R. James, R. Jhaveri,I. Jin, H. Kam,E. Karl, C. Kenyon, M. Liu, Y. Luo,R. Mehandru,S. Morarka,L. Neiberg,P. Packan, A. Paliwal, C. Parker, P. Patel, R. Patel,C. Pelto,L. Pipes,P. Plekhanov, M. Prince, S. Rajamani, J. Sandford,B. Sell, S. Sivakumar, P. Smith, B. Song, K. Tone,T. Troeger,J. Wiedemer, M. Yang, K. Zhang
2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) (2014)
Cited343Views0EIWOSBibtex
343
0
Fact Sheet Intel Talks about Future Technologies for Processors , Reveals New Details about 22 nm 3-D Tri-Gate Transistors
Mim Capacitor,C Auth, C Allen, A Blattner,D Bergstrom,M Brazier,M Bost,M Buehler,V Chikarmane,T Ghani,T Glassman,R Grover, W Han, D Hanken,M Hattendorf,P Hentges,R Heussner,J Hicks,D Ingerly, P Jain,S Jaloviar,R James, D Jones,J Jopling,S Joshi, C Kenyun, H Liu, R Mcfadden,B Mcintyre,J Neirynck,C Parker,L Pipes,I Post, S Pradhan,M Prince,S Ramey, T Reynolds, J Roester, J Sanford,J Seiple, P Smith, C Thomas, D Towner,T Troeger, G Weber,P Yashar,K Zawadzki,K Mistry
semanticscholar（2012）
Cited0Views0Bibtex
0
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Author Statistics

#Papers: 9

#Citation: 2849

H-Index: 7

G-Index: 7

Sociability: 5

Diversity: 1

Activity: 0

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