Pushkar Ranade - Department of Electrical Engineering and Computer Sciences, University of California at Berkeley

基本信息

Career Trajectory

Bio

Pushkar Ranade received the B.Eng. degree (with distinction) in metallurgy from the University of Pune, Pune, India in 1996 and the M.S. and Ph.D. degrees in materials science and engineering from the University of California, Berkeley, in 1998 and 2002, respectively. In 2002, he was with IBM Corporation's T.J. Watson Research Center, Yorktown Heights, NY. He is currently with Intel Corporation, Hillsboro, OR. He has authored or coauthored over 30 scientific publications and has three U.S. patents pending. His doctoral research was in the area of sub-100-nm MOS transistor design and fabrication and involved the integration of novel gate stack materials and processes and ultrashallow junction fabrication techniques.

Research Interests

Papers共 43 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

Low Power ARM® Cortex™-M0 CPU and SRAM Using Deeply Depleted Channel (DDC) Transistors with Vdd Scaling and Body Bias

V. Agrawal, N. Kepler,D. Kidd, G. Krishnan,S. Leshner, T. Bakishev,D. Zhao,P. Ranade,R. Roy, M. Wojko,L. Clark,R. Rogenmoser, M. Hori,T. Ema, S. Moriwaki,T. Tsuruta, T. Yamada,J. Mitani, S. Wakayama

2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)（2013）

Cited5Views0EIWOSBibtex

超低電圧動作を可能にするチャネルエンジニアリング(IEDM特集(先端CMOSデバイス・プロセス技術))

和司藤田, 泰伸鳥居,充明堀,純志王,L. Shifren,P. Ranade,雅樹中川,堅一岡部, 利紀三宅,克明大越, 正樹蔵前,年史森, 智也鶴田, S. Thompson,泰示江間

siam international conference on data mining（2012）

Cited23Views0Bibtex

A Highly Integrated 65-Nm Soc Process with Enhanced Power/Performance of Digital and Analog Circuits

L. T. Clark,D. Zhao,T. Bakhishev,H. Ahn, E. Boling, M. Duane, K. Fujita,P. Gregory,T. Hoffmann, M. Hori, D. Kanai,D. Kidd, S. Lee, Y. Liu, J. Mitani, J. Nagayama,S. Pradhan,P. Ranade,R. Rogenmoser,L. Scudder,L. Shifren,Y. Torii, M. Wojko,Y. Asada,T. Ema, S. Thompson

2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2012）

Cited29Views0EIWOSBibtex

Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-power Applications

K. Fujita,Y. Torii, M. Hori, J. Oh,L. Shifren,P. Ranade,M. Nakagawa,K. Okabe, T. Miyake,K. Ohkoshi,M. Kuramae, T. Mori, T. Tsuruta,S. Thompson,T. Ema

2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2011）

Cited63Views0EIWOSBibtex

45Nm High-k + Metal Gate Strain-Enhanced Transistors

C. Auth,A. Cappellani, J. -S. Chun,A. Dalis, A. Davis,T. Ghani,G. Glass,T. Glassman, M. Harper,M. Hattendorf,P. Hentges,S. Jaloviar,S. Joshi,J. Klaus,K. Kuhn, D. Lavric,M. Lu, H. Mariappan,K. Mistry, B. Norris, N. Rahhal-orabi,P. Ranade,J. Sandford,L. Shifren, V. Souw,K. Tone, F. Tambwe, A. Thompson, D. Towner,T. Troeger, P. Vandervoom, C. Wallace,J. Wiedemer,C. Wiegand

2008 SYMPOSIUM ON VLSI TECHNOLOGYpp.99-+, (2008)

Cited0Views0EIWOSBibtex

High Performance Hi-K + Metal Gate Strain Enhanced Transistors on (110) Silicon

P. Packan,S. Cea,H. Deshpande,T. Ghani,M. Giles,O. Golonzka,M. Hattendorf,R. Kotlyar,K. Kuhn,A. Murthy,P. Ranade,L. Shifren,C. Weber,K. Zawadzki

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST（2008）

Cited77Views0EIWOSBibtex

CMOS Device with Dual-Epi-channels and Self-Aligned Contacts and Manufacturing Processes

P. Ranade, K. Zawadzki

semanticscholar（2008）

Cited0Views0Bibtex

45nm High-k + metal gate strain-enhanced transistors

C Auth,Annalisa Cappellani, J S Chun,A Dalis, Allen P Davis,Tahir Ghani, G B J Glass,T Glassman,Mark A Harper,M Hattendorf, P J Hentges,S Jaloviar, S C Joshi,J W Klaus,Kelin J Kuhn, D Lavric,M Lu, H Mariappan,K Mistry, B J Norris,Nadia Rahhalorabi,P Ranade,J Sandford,Lucian Shifren, V Souw,K Tone, F Tambwe, A C Thompson, David J Towner,T Troeger,P Vandervoorn,Claudina Y Wallace,J Wiedemer,Clyde E Wiegand

mag（2008）

Cited376Views0Bibtex

376

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry,C. Allen,C. Auth,B. Beattie,D. Bergstrom,M. Bost,M. Brazier,M. Buehler,A. Cappellani,R. Chau,C. -H. Choi,G. Ding,K. Fischer,T. Ghani,R. Grover,W. Han, D. Hanken, M. Hatttendorf,J. He,J. Hicks, R. Huessner,D. Ingerly,P. Jain,R. James, L. Jong,S. Joshi,C. Kenyon,K. Kuhn, K. Lee, H. Liu,J. Maiz,B. McIntyre,P. Moon,J. Neirynck, S. Pei,C. Parker,D. Parsons,C. Prasad,L. Pipes,M. Prince,P. Ranade, T. Reynolds,J. Sandford, L. Schifren,J. Sebastian,J. Seiple, D. Simon,S. Sivakumar,P. Smith, C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki

2007 IEEE International Electron Devices Meeting（2007）

Cited1647Views0EIWOSBibtex

1647

A 45nmlogictechnology Withhigh-K+metal GateTransistors, Strained Silicon, 9cuinterconnect Layers, 193nmdrypatterning, And100%pb-Free Packaging

K. Mistry, C. C. Allen,C. Auth, Brian Beattie,D. Bergstrom,M. Bost,M. Brazier, Markus J. Buehler,A. Cappellani,R. Chau, Changhwan Choi, G. Ding, K. Fischer,T. Ghani,R. Grover, Weihua Han, Dennis G. Hanken,M. Hattendorf,J. Hicks, R. Huessner,D. Ingerly, Pulkit Jain,R. James, Lee Soo Jong, Shalik Ram Joshi,C. Kenyon,Kelin J. Kuhn, Kyung Wook Lee, H. Liu,J. Maiz,B. McIntyre, Peter C. Moon,J. Neirynck,Sangwoo Pae,C. Parker,D. Parsons,C. Prasad, Leonard C. Pipes, M. B. Prince,P. Ranade, T.E. Reynolds,J. Sandford,L. Shifren,J. Sebastián, J. V. Seiple, Dan Simon,S. Sivakumar, P. Smith, Christopher W. Thomas,T. Troeger,P. Vandervoorn, Leonid Oliker,K. Zawadzki

openalex（2007）

Cited0Views0Bibtex

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