Thomas Ernst

Thomas Ernst (S'99–A'00–M'03) received the M.Sc. and Ph.D. degrees from the National Polytechnics Institute of Grenoble, Grenoble, France, in 1997 and 2000, respectively. From 1997 to 2000, he worked on advanced silicon-on-insulator (SOI) low-voltage and low-power CMOS electrical characterization, simulation, and modeling with L'Institut de Microélectronique, Électromagnétisme et Photonique Laboratory and STMicroelectronics. He then joined CEA–Laboratoire d'Electronique et de Technologie de l'Information (LETI), MINATEC, Grenoble, to develop novel strained-channel CMOS architectures for the 32-nm technology, where, particularly, he was leading strained SOI and SiGeOI CMOS integration. Since 2005, he has been in charge of 3-D stacked-channel CMOS device developments with LETI. His expertise is in the area of novel CMOS device fabrication technology and short-channel device analytical modeling and electrical characterization. He is the author or coauthor of over 75 technical journal papers and communications at international conferences on CMOS device integration, modeling, and characterization. Dr. Ernst has been a European Solid State Device Research Conference committee member since 2005.