Yongkang Han - Zhejiang Lab | 人才画像

基本信息

Career Trajectory

Bio

Yongkang Han received the M.Eng. degree in integrated circuit engineering from Fudan University, Shanghai, China, in 2021. He currently works at Zhangjiang Laboratory, Shanghai, as an Analog IC Design Engineer. He is responsible for new architecture memory research and development.

Research Interests

Papers共 11 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

A 9mb HZO-Based Embedded FeRAM with 10-Cycle Endurance and 5/7ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier

Qiqiao Wu,Yue Cao,Qing Luo,Haijun Jiang,Zhongze Han,Yongkang Han,Chunmeng Dou,Hangbing Lv,Qi Liu,Jianguo Yang,Ming Liu

IEEE JOURNAL OF SOLID-STATE CIRCUITSno. 1 (2024): 208-218

Cited6Views0EIWOSBibtex

A 1024-Spin Scalable Ising Machine with Capacitive Coupling and Progressive Annealing Method for Combination Optimization Problems

Yixuan Liu,Zhongze Han,Qiqiao Wu,Honghu Yang, Yue Cao,Yongkang Han,Haijun Jiang,Xiaoyong Xue,Jianguo Yang,Xiaoyang Zeng

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFSno. 12 (2024): 5009-5013

Cited0Views0EIWOSBibtex

A Novel Neuromorphic Hardware Using Area-Efficient Chain RRAM-Based Synapses and Compact Neurons with (Anti-) Integration Scheme

Qiqiao Wu,Honghu Yang,Yixuan Liu, Yue Cao,Yongkang Han,Haijun Jiang,Keji Zhou, Hailan Yi,Jianguo Yang,Qi Liu

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2024)

Cited0Views0EIWOSBibtex

Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits

Donglin Zhang,Honghu Yang, Yue Cao,Zhongze Han,Yixuan Liu,Qiqiao Wu,Yongkang Han,Haijun Jiang,Jianguo Yang

Micromachines（2023）

Cited0Views0WOSBibtex

An ADC-Less RRAM-Based Computing-in-Memory Macro with Binary CNN for Efficient Edge AI

Yi Li,Jia Chen,Linfang Wang,Woyu Zhang,Zeyu Guo,Jun Wang,Yongkang Han,Zhi Li,Fei Wang,Chunmeng Dou,Xiaoxin Xu,Jianguo Yang,Zhongrui Wang,Dashan Shang

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS（2023）

Cited17Views0EIWOSBibtex

A 9mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier

Jianguo Yang,Qing Luo,Xiaoyong Xue,Haijun Jiang,Qiqiao Wu,Zhongze Han,Yue Cao,Yongkang Han,Chunmeng Dou,Hangbing Lv,Qi Liu,Ming LiU

2023 IEEE International Solid-State Circuits Conference (ISSCC)pp.1-3, (2023)

Cited0Views0EIWOSBibtex

Probabilistic Circuit Implementation Based on P-Bits Using the Intrinsic Random Property of RRAM and P-Bit Multiplexing Strategy

Yixuan Liu,Qiao Hu,Qiqiao Wu,Xuanzhi Liu,Yulin Zhao,Donglin Zhang,Zhongze Han,Jinhui Cheng,Qingting Ding,Yongkang Han,Bo Peng,Haijun Jiang,Xiaoyong Xue,Hangbing Lv,Jianguo Yang

Micromachines（2022）

Cited5Views0WOSBibtex

Cache-Major: A Hardware Architecture and Scheduling Policy for Improving DRAM Access Efficiency in GEMV

Jinhui Cheng,Xuanzhi Liu,Yue Cao, Wenjun Zhang,Zhongze Han, Bo Peng,Yixuan Liu,Donglin Zhang,Yongkang Han,Xiaoxin Xu,Jianguo Yang

2022 IEEE 16th International Conference on Solid-State &amp Integrated Circuit Technology (ICSICT) (2022)

Cited0Views0EIWOSBibtex

0.1V Low Power Bandgap Reference for RRAM Storage Applications

Yongkang Han,Wenjun Zhang,Yue Cao,Haijun Jiang,Ruixi Zhou,Xiaoxin Xu,Jianguo Yang

2022 IEEE 16th International Conference on Solid-State &amp Integrated Circuit Technology (ICSICT) (2022)

Cited0Views0EIWOSBibtex

Novel 15T SRAM Cell for Low Voltage High Reliability Application

Yongkang Han,Yulin Zhao,Qiao Hu,Xuanzhi Liu,Bo Peng,Haijun Jiang,Jianguo Yang,Xiaoyong Xue

2021 IEEE 14th International Conference on ASIC (ASICON)（2021）

Cited0Views0EIWOSBibtex

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