Analysis of Triggering Behaviour of High Voltage CMOS LDMOS Clamps and SCRs During ESD Induced Latch-UpM. Heer,V. Dubec,S. Bychikhin,D. Pogany,E. Gornik,M. Frank,A. Konrad,J. SchulzMicroelectronics Reliability（2006）引用 6|浏览11AI 理解论文溯源树样例生成溯源树，研究论文发展脉络Chat Paper正在生成论文摘要
