A 32 Nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers

Reid Riedlinger, Ron Arnold,Larry Biro,Bill Bowhill,Jason Crop,Kevin Duda, Eric S. Fetzer,Olivier Franza, Tom Grutkowski, Casey Little,Charles Morganti, Gary Moyer, Ashley Munch,Mahalingam Nagarajan, Cheolmin Parks, Christopher Poirier, Bill Repasky, Edi Roytman,Tejpal Singh, Matthew W. Stefaniw

IEEE journal of solid-state circuits（2012）

Cited 144|Views63

Key words

Architectural memory ordering,random logic synthesized and placed circuitry (RLS),structured datapath (SDP),small signal arrays (SSA),regional clock buffer (RCB),instruction buffer logic (IBL),integer execution unit (IEU),first level data (FLD),quick path interconnect (QPI),double error correction,triple error detection (DECTED),second level data TLB (DTB),failure in thousands (FIT),First level instruction (FLI),home agent,instruction level parrallelism (ILP),Itanium processor family,last level cache (LLC),memory controller (MC),mid level data cache (MLD),mid level instruction cache (MLI),ordering CZQueue (OZQ),Intel scalable memory interconnect (SMI),register file (RF),single error correction,double error detection (SECDEC),thermal design power (TDP),translation look-aside buffer (TLB)

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined