Design and Verification of Logic Block Circuit in an SOI-based FPGA

Xiaowei Han,Chen, S.L.,Lihua Wu,Yan Zhao

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology（2010）

Cited 1|Views3

Key words

field programmable gate arrays,logic circuits,random-access storage,silicon-on-insulator,LUT,SOI,Xilinx Spartan FPGA,design,distributed RAM mode,logic block circuit,logic propagation delay,multi-mode logic cells,verification

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