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A 32–48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 Nm CMOS Technology

IEEE Journal of Solid-State Circuits(2015)

Univ Calif Los Angeles

Cited 42|Views35
Abstract
A power-efficient transmitter is proposed using a multiphase serializer, multiphase dividers using injection-locked oscillators, and a high-speed multiplexing structure to relax the timing constraints. With this architecture, bit times near 1 FO-4 gate delay are achieved using only nominal devices in a 65 nm CMOS technology. The divider and serializer operate over a wide range of data rates between 32 and 48 Gb/s limited mainly by the operation range of the frequency synthesizer. The transmitter occupies 0.4 mm(2) and consumes 88 mW from a 1.2 V supply which corresponds to 1.8 pJ/bit of power efficiency.
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Key words
Frequency divider,low power,multiphase sampling,multiplexer,quarter rate,serial link,serializer,transmitter
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