A hierarchical switch matrix and interconnect resources test in Virtex-5 FPGA
ISIC（2014）
关键词
field programmable gate arrays,integrated circuit interconnections,integrated circuit testing,ir architecture,pip-ps,spartan series fpga,virtex 7-series,virtex-2 series,virtex-4 series,virtex-5 fpga,virtex-5 series,virtex-6 series,virtex-series,xc4000 fpga,xc5lx110t,bitstream readback,boundary scan,fault mapping method,hierarchical sm,hierarchical switch matrix,in-house developed test system,interconnect resources test,programmable-interconnect-point programmable switches,repeatable building blocks,wire segments,fpga,virtex-5,interconnect resources,routing,switches
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