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Bias Temperature Instability Investigation of Double-Gate FinFETs

Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)(2014)

Cited 3|Views3
Key words
MOSFET,integrated circuit reliability,negative bias temperature instability,silicon-on-insulator,SOI wafers,bias temperature instability investigation,bond breaking trap centers,crystallographic sidewall orientation,double gate FinFET,fin width dependence,negative stress bias,sidewall device channel region,silicon on insulator wafers,surface bonds
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