10Nm FINFET Technology for Low Power and High Performance Applications

D. Guo,H. Shang,K. Seo,B. Haran,T. Standaert,D. Gupta,E. Alptekin,D. Bae,G. Bae,D. Chanemougame,K. Cheng,J. Cho,B. Hamieh,J. Hong,T. Hook, J. Jung,R. Kambhampati,B. Kim,H. Kim,K. Kim,T. Kim,D. Liu,H. Mallela,P. Montanini,M. Mottura,S. Nam, L. Ok,Y. Park,A. Paul,C. Prindle,R. Ramachandran,V. Sardesai,A. Scholze,S. Seo,R. Southwick,J. Strane,X. Sun,G. Tsutsui,N. Tripathi,R. Vega,M. Weybright,R. Xie,C. Yeh,H. Bu,S. Burns,D. Canaperi,M. Celik,M. Colburn,H. Jagannathan, S. Kanakasabaphthy,W. Kleemeier,L. Liebmann,D. Mcherron,P. Oldiges,V. Paruchuri,T. Spooner,J. Stathis,R. Divakaruni, T. Gow, J. Jacoponi, J. Jenq,R. Sampson, W. Yang,M. Khare

2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)（2014）

引用 8|浏览82

关键词

CMOS integrated circuits,MOSFET,SRAM chips,lithography,low-power electronics,CMOS platform technology,CPP,FinFET technology,MWF gate stack,RDF,SNM,SOI substrates,bulk substrates,contacted poly pitch,lithography,metallization pitch,multipatterning technology,multiworkfunction gate stack,optical patterning limits,random dopant fluctuation,self-aligned processes,size 10 nm,size 48 nm,static noise margin,variability degradation,voltage 0.75 V,voltage 140 mV

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要