A 390-Mm/sup 2/, 16-Bank, 1-Gb DDR SDRAM with Hybrid Bitline Architecture

T Kirihata,G Mueller,B Ji,G Frankowsky,JM Ross,H Terletzki,DG Netis,O Weinfurtner,DR Hanson,G Daniel,LLC Hsu,DW Storaska,AM Reith,MA Hug,KP Guay,M Selz,P Poechmueller,H Hoenigschmid,MR Wordeman

IEEE Journal of Solid-State Circuits（1999）

引用 42|浏览9

关键词

double-data-rate (DDR),dynamic random access memory (DRAM),hierarchical column-select-line (CSL),hybrid bitline,low voltage,1 Gb,prefetch,synchronous DRAM

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