Performance Improvements in High-Density DRAM Application Using 0.15 Μm Body-Contacted SOI Technology
Wakefield, MA（2000）
Key words
CMOS memory circuits,DRAM chips,MOSFET,SRAM chips,integrated circuit measurement,isolation technology,silicon-on-insulator,0.15 micron,256 Mbit,BC-SOI MOSFET,SOI CMOS technology,SOI SDRAM,Si-SiO2,body-contacted SOI structure,body-contacted SOI technology,body-potential increase suppression,bulk CMOS technology compatibility,floating-body effects,high-density DRAM application,isolation process,process technology,refresh characteristics,shallow trench isolation,silicon-on-insulator CMOS technology,thin-silicon film,well contact
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