A 0.127 Μm2 High Performance 65nm SOI Based Embedded DRAM for On-Processor Applications

G. Wang,K. Cheng, H. Ho,J. Faltermeier,W. Kong, H. Kim,J. Cai, C. Tanner,K. McStay, K. Balasubramanyam,C. Pei, L. Ninomiya, X. Li,K. Winstel,D. Dobuzinsky, M. Naeem, R. Zhang, R. Deschner,M. J. Brodsky, S. Allen, J. Yates, Y. Feng,P. Marchetti, C. Norris, D. Casarotto,J. Benedict, A. Kniffin, D. Parise,B. Khan, J. Barth,P. Parries,T. Kirihata,J. Norum,S. S. Iyer

2006 International Electron Devices Meeting（2006）

Cited 36|Views3

Key words

DRAM chips,capacitors,low-power electronics,nanoelectronics,silicon-on-insulator,2 MByte,2.2 nm,65 nm,DRAM cell,deep trench capacitor,dual stress liner,gate oxide pass transistor,silicon-in-insulator,trench side wall spacer

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