A High-Resolution All-Digital Phase-Locked Loop with Its Application to Built-in Speed Grading for Memory
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)（2008）
Key words
UHF oscillators,built-in self test,digital phase locked loops,phase detectors,BIST,PFD,all-digital phase-locked loop,binary search process,built-in self-test,built-in speed grading,clock generator,digitally controlled oscillator,frequency 70 MHz to 725 MHz,latch-based sense amplifier,phase-frequency detector
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