55 Nm Capacitor-Less 1T DRAM Cell Transistor with Non-Overlap Structure
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST（2008）
Key words
DRAM chips,bipolar transistors,scaling circuits,BJT-based transistor scheme,TCAD analysis,capacitor-less 1T DRAM cell transistor,junction leakage suppression,nonoverlap structure,retention time,size 55 nm,temperature 85 C,time 80 ms,transistor scalability
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