Comprehensive Layout and Process Optimization Study of Si and III-V Technology for Sub-7Nm Node

C. Y. Kang,R-H. Baek,T-W Kim,D. Ko,D-H. Kim,T. Michalak,C. Borst,D. Veksler,G. Bersuker,R. Hill,C. Hobbs,P. D. Kirsch

2013 IEEE International Electron Devices Meeting（2013）

Cited 1|Views10

Key words

III-V semiconductors,SRAM chips,elemental semiconductors,integrated circuit layout,optimisation,silicon,BSIM models,III-V device compact,III-V device performance,III-V technology,SRAM read time,Si,Si technology,comprehensive layout,geometry-dependent parasitic RC,process optimization,ring oscillator delay,size 7 nm

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