Retention Time Optimization for Edram in 22nm Tri-Gate CMOS Technology

Yih Wang,Umut Arslan,Nabhendra Bisnik,Ruth Brain,Swaroop Ghosh,Fatih Hamzaoglu,Nick Lindert,Mesut Meterelliyoz,Joodong Park,Shigeki Tomishima,Kevin Zhang

2013 IEEE International Electron Devices Meeting（2013）

Cited 22|Views89

Key words

CMOS integrated circuits,DRAM chips,low-power electronics,optimisation,system-on-chip,Gbit eDRAM,critical circuits,design cooptimization,eDRAM bitcell,high performance eDRAM technology,high-performance trigate CMOS SoC technology,low-power 22nm trigate CMOS SoC technology,noise reduction circuit techniques,retention time optimization,size 22 nm,temperature 95 C

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