High Density 3D Integration Using CMOS Foundry Technologies for 28 Nm Node and Beyond

J. C. Lin,W. C. Chiou,K. F. Yang,H. B. Chang, Y. C. Lin,E. B. Liao,J. P. Hung,Y. L. Lin, P. H. Tsai, Y. C. Shih,T. J. Wu, W. J. Wu,F. W. Tsai,Y. H. Huang, T. Y. Wang,C. L. Yu,C. H. Chang,M. F. Chen,S. Y. Hou,C. H. Tung,S. P. Jeng,Doug C. H. Yu

International Electron Devices Meeting（2010）

引用 74|浏览39

关键词

CMOS integrated circuits,integrated circuit reliability,nanoelectronics,semiconductor device reliability,three-dimensional integrated circuits,wiring,3D IC technology,3D integration scheme reliability,CMOS foundry technology,Si foundry technology,critical 3D integrated circuit enabling technology,high density 3D integration,high-density three dimensional chip integration structures,microbump process,redistribution layer,through silicon via,wafer thinning,wiring

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