High-density 3D Electronic-Photonic Integration

V. Stojanović,K. T. Settaluri, S. Lin,S. Moazeni,E. Timurdogan,C. Sun,M. Moresco,Z. Su,Y-H. Chen,G. Leake, D. LaTulipe,C. McDonough,J. Hebding,D. Coolbaugh,M. Watts

2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S)（2015）

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关键词

3D electronic-photonic integration,integration complexity,Luxtera's process,monolithic integration,Oracle,ST Micro,photonic chips,electronic chips,face-to-face microbump-copper-pillar bonding,optimized photonics,interconnection parasitics,electrical wirebond,chip-to-chip bumps,photonic components,photonic devices,electronic wafers,photonic wafers,photonic SOI wafer,CMOS wafer,tight-pitch shallow through-oxide vias,TOV,parasitic capacitance,on-chip deembedding structures,energy efficiency,transmitter sensitivity,receiver sensitivity,optical power,photonic transceiver modules,modulator driver,thermal-tuning lock circuitry,deserializer,thermal lock circuitry,optical chip-to-chip link,energy consumption,on-chip calibration,single mode optical fiber,optical energy,size 45 nm,Si

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