LP-HP Nanoscale FinFET-CMOS Design Via Source/drain Engineering
New Paltz, NY（2008）
Key words
CMOS integrated circuits,MOSFET,integrated circuit design,laser beam annealing,nanoelectronics,CMOS design,SIA roadmap,laser annealing,low-power-high-performance nanoscale FinFET,source-drain dopants
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