A Shorted Global Clock Design for Multi-Ghz 3D Stacked Chips.
VLSIC（2012）
Key words
DRAM chips,clocks,delay lock loops,silicon-on-insulator,three-dimensional integrated circuits,2-strata eDRAM test chip,3D stacked chip,DLL-based technique,IBM 45nm SOI 3D technology,clock tree,delay-locked loop circuit,global clock design,global clock distribution technique,permit at-speed testing,size 45 nm,3D chip,GHz,VLSI,clock distribution
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