80Kb 10ns Read Cycle Logic Embedded High-K Charge Trap Multi-Time-Programmable Memory Scalable to 14nm FIN with No Added Process Complexity

Janakiraman Viraraghavan,Derek Leu,Balaji Jayaraman,Alberto Cestero, Robert Kilker,Ming Yin,John Golz,Rajesh R. Tummuru,Ramesh Raghavan,Dan Moy,Thejas Kempanna,Faraz Khan,Toshiaki Kirihata,Subramanian Iyer

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)（2016）

Cited 13|Views87

Key words

overwrite protection,multistep verification,high-K transistor,charge trapping,FIN,MTPM,embedded high-K charge trap multitime programmable memory scalable,read cycle logic

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