Accurate Performance Evaluation for the Horizontal Nanosheet Standard-Cell Design Space Beyond 7nm Technology
2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2017）
Key words
improved power-performance,area scaling,device-performance entitlement,high-density chip designs,gate-resistance,cell heights,performance-aware designs,smaller track cells,horizontal nanosheet standard-cell design,vertically-stacked horizontal gate-all-around nanosheet structures,high-performance chip designs,unique nanosheet challenges,M1 power staples,size 7.0 nm
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