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3D System Integration on 300 Mm Wafer Level: High-aspect-ratio TSVs with Ruthenium Seed Layer by Thermal ALD and Subsequent Copper Electroplating

Microelectronic Engineering(2019)

Cited 19|Views74
Key words
3D-integration,Through-silicon via,Copper TSV fill,Atomic layer deposition,Ruthenium seed layer,Tantalum nitride diffusion barrier
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