First Transistor Demonstration of Thermal Atomic Layer Etching: InGaAs FinFETs with Sub-5 Nm Fin-width Featuring in Situ ALE-ALD
2018 IEEE International Electron Devices Meeting (IEDM)（2018）
Key words
thermal atomic layer etching,InGaAs-based III-V heterostructures,thermal ALE technique,atomic layer deposition,n-channel FinFETs,InGaAs FinFET,ALE-ALD process,single vacuum chamber,self-aligned n-channel FinFET,MOS interface,voltage 0.5 V,InGaAs
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