Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs Applications

P. -J. Sung,C. -Y. Chang, L. -Y. Chen,K. -H. Kao,C. -J. Su, T. -H. Liao,C. -C. Fang,C. -J. Wang,T. -C. Hong, C. -Y. Jao,H. -S. Hsu,S. -X. Luo,Y. -S. Wang, H. -F. Huang, J. -H. Li,Y. -C. Huang,F. -K. Hsueh,C. -T. Wu,Y. -M. Huang,F. -J. Hou,G. -L. Luo,Y. -L. Shen,W. C. -Y. Ma,K. -P. Huang,K. -L. Lin,S. Samukawa,Y. Li,G. -W Huang,Y. -J. Lee,J. -Y. Li,W. -F. Wu,J. -M. Shieh,T. -S. Chao,W. -K. Yeh,Y. -H. Wang

2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2018）

Cited 12|Views63

Key words

stacked n/p-channel FET,poly-Si NS,SoP/3D-IC applications,nanosheet layer numbers,smooth surface roughness,system-on-panel,NS layer numbers,low leakage current,single channel devices,dry etching process,vertically stacked junctionless nanosheets,vertically stacked junctionless CMOS inverter,voltage transfer characteristic matching,Si

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