2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications

J. G. Alzate,U. Arslan,P. Bai,J. Brockman,Y. J. Chen,N. Das,K. Fischer,T. Ghani,P. Heil,P. Hentges,R. Jahan,A. Littlejohn, M. Mainuddin,D. Ouellette, J. Pellegren,T. Pramanik,C. Puls,P. Quintero,T. Rahman,M. Sekhar,B. Sell,M. Seth,A. J. Smith, A. K. Smith,L. Wei,C. Wiegand,O. Golonzka,F. Hamzaoglu

2019 IEEE International Electron Devices Meeting (IEDM)（2019）

Cited 110|Views17

Key words

array-level MTJ process,reliability requirements,STT-MRAM operation,scaled-size MTJ devices,L4 Cache specifications,etch process,array-level tail failure events,array-level demonstration,STT-MRAM process,L4 cache application,ECC-correctable bit fail rates,memory size 2.0 MByte

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