15.4 A 22nm 2mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices
2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC)（2020）
Key words
cell arrays,BL-IN-OUT muitibit computing scheme,BLIOMC scheme,input-aware muitibit BL clamping,scrambled 2's complement weight mapping,S2C S2CWM,input-aware source-line voltage biasing,SL IA-SLVB,dual-bit small-offset current-mode sense amplifier,positive-negative-split weight-mapping,1T1R cells,current density,wide metal lines,BL-clamping voltage,activated WLs,multibit CNNs,multibit CNNs,neural networks,system wake-up,multiply-and-accumulate computing,energy-efficiency,nonvolatile computing-in-memory,4bIN-4bW-11bOUT compute precisions,S2CVC,S2C value combiner,compact array area,area overhead,nvCIM macros,high-inference accuracy,binary input,tiny AI edge devices,multibit MAC computing,ReRAM compute-in-memory macro,size 22.0 nm,time 9.8 ns to 18.3 ns,storage capacity 2 Mbit,storage capacity 4 bit
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