Concepts and geometries for the next generation of precision heterodyne optical encoders
semanticscholar（2016）
Abstract
The fabrication of integrated circuits and solidstate memory relies on lithographic printing of overlaying patterns onto a semiconductor wafer. The manufacturing process may consist of more than 40 cycles, with each cycle defining a specific layer. Lithographic exposures require stage motions during a continuous projection, with the requirement that new patterns are registered with previous layers to much less than the minimum feature size or critical dimension (CD) of individual transistors, currently at 16 nm [1]. Double-exposure techniques permit an overlay error of no more than 15% of the CD, with about 20% of this number or 3% of the CD or 0.5 nm allocated for stage metrology [2].
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