Dynamic Memory and Sequential Logic Design Using Negative Capacitance FinFETs.
International Symposium on Circuits and Systems（2020）
关键词
area-power-delay-product,dynamic memory,sequential logic design,negative capacitance FinFETs,low-power VLSI circuits,low-area dynamic random access memory,sequential logic circuits,leakage currents,dynamic storage-based logic design style,circuit-level solutions,eDRAM circuits,BS-FinFET static-storage,NC-FinFET device,area overhead,data retention time,DS latch,flip-flop,baseline FinFET,ultra-low-power dynamic random access memory,size 14.0 nm
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