A Scalable Architecture for CNN Accelerators Leveraging High-Performance Memories
2020 IEEE High Performance Extreme Computing Conference (HPEC)（2020）
Key words
scalable architecture,CNN accelerators leveraging High-Performance memories,FPGA-based accelerators,High-Performance Memory,greater bandwidth,standard DDR4 DRAM,design challenges,higher bandwidth mismatch,FPGA cores,convolutional neural network accelerators,high-level synthesis,available memory bandwidth
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