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Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

Y. Kim,S-C Seo,S. Consiglio,P. Jamison, H. Higuchi,M. Rasch,E. Y. Wu,D. Kong,I Saraf,C. Catano,R. Muralidhar,S. Nguyen, S. DeVries,O. Van der Straten,M. Sankarapandian,R. N. Pujari,A. Gasasira, S. M. Mcdermott,H. Miyazoe, D. Koty, Q. Yang, H. Yan,R. Clark,K. Tapily,S. Engelmann, R. R. Robison,C. Wajda,A. Mosden,T. Tsunomura, R. Soave,N. Saulnier,W. Haensch,G. Leusink, P. Biolsi,V Narayanan,T. Ando

IEEE ELECTRON DEVICE LETTERS（2021）

Cited 7|Views81
Key words
Resistance,Reservoirs,Plasmas,Switches,Electrodes,Hafnium oxide,Standards,Analog compute,cross-bar array,plasma process,ReRAM
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