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Customized Parallel Reliability Testing Platform With Multifold Throughput Enhancement For Intel Stressing Tests

P. Xiao, H. Hadziosmanovic, M. Klessens,R. Jiang, J. Ortega, D. Schroeder, James Palmer, I. Tsameret

2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)(2021)

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Key words
Parallel testing,wafer level,throughput enhancement,customization,modularization
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