A 1-to-112gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET

Aida Varzaghani,Bardia Bozorgzadeh, Jack Lam,Ankush Goel,Xiaobin Yuan,Mohamed Elzeftawi,Mehran Izad,Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi,Shahrzad Naraghi,Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos,Shwetabh Verma,Stefanos Sidiropoulos

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）

引用 5|浏览11

关键词

quad transceiver,flexible clocking scheme,low power transceiver,data rate,DSP based wireline transceiver,Ethernet,PCI applications,protocols,size 5.0 nm

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