Cache-Major: A Hardware Architecture and Scheduling Policy for Improving DRAM Access Efficiency in GEMV

Jinhui Cheng,Xuanzhi Liu,Yue Cao, Wenjun Zhang,Zhongze Han, Bo Peng,Yixuan Liu,Donglin Zhang,Yongkang Han,Xiaoxin Xu,Jianguo Yang

2022 IEEE 16th International Conference on Solid-State &amp Integrated Circuit Technology (ICSICT)（2022）

引用 0|浏览17

关键词

architectural system,byte rate 112.34 MByte/s,cache-major policy,critical operations,dram access efficiency,DRAM address locality,effective bandwidth,efficient cache,engineering applications,float-point matrix,GEMV problem,general matrix-vector multiplication,hardware architecture,high bandwidth cache,high performance computing,high-performance GEMV computation,highly customized memory controller,out-of-order access,scheduling policy,system access bandwidth

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要