A 65nm 60mw Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for Mm-Wave Applications.
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2023）
Key words
2 on-chip area,65nm 60mW dual-loop adaptive digital beamformer,65nm CMOS dissipates 60mW,adaptive beamformer,adaptive sidelobe canceller,arrival estimation,CORDIC-based QR-iteration,DOA estimation loop,efficient ESPRIT DOA estimation,energy efficiency,frequency 100.0 MHz,high energy-efficiency,mm-wave applications,mm-wave baseband digital beamformer,on-chip direction,On-Chip DOA Estimation,optimized sidelobe cancellation,power 60.0 mW,sidelobe cancellation loop,size 65.0 nm
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