A 0.004-mm(2) 0.7-V 31.654-mu W BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL

2022 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS（2022）

引用 0|浏览14

关键词

Binary-phase-shift-keying (BPSK) demodulator, dual-path loop, self-biased phase-locked loop (PLL), CMOS

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要