An Innovative Program Scheme for Reducing Z-Interference in Charge-Trap-Based 3-D NAND Flash Memory
IEEE TRANSACTIONS ON ELECTRON DEVICES（2023）
Key words
Flash memories,Logic gates,Electron traps,Interference,Three-dimensional displays,Threshold voltage,Simulation,3-D NAND flash,charge trap,program scheme,technology computer-aided design (TCAD) simulation,z-direction interference (Z-interference)
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