GDI Logic Based Design of Decoder Circuit for Low Power Applications

In this paper a novel design of a low power based 3:8 decoder circuit is proposed for high speed operations. Decoders having great application usage in the field of Address Decoding for Memory devices, Control Logic for Processors and Controllers, etc., make them an essential part of the design where further power and area reduction can be achieved. The proposed design utilizes the Gate Diffusion Technique (GDI) to recreate the conventional decoder circuit. Cadence Virtuoso tool is used for design of the proposed circuit on 90nm technology. Performance analysis of power, delay and layout area are observed and tabulated for comparison. Overall the proposed design has 60% less power, 55.4% reduced delay & takes 62.% less area when compared to CMOS design decoder circuit. The proposed design can be used to optimize both area and power consumption in various low-power applications such as mobile devices, IoT devices, and other battery-operated systems.