第2世代10nm DRAMプロセスにおけるスキュー耐性,低電力,速度ブースティング技術を用いたハイブリッドバンクアーキテクチャによる22.2 8.5Gb/s/pin 12GB-LPDDR5 SDRAM【JST・京大機械翻訳】
Hyung‐Joon Chi,Chang‐Kyo Lee,Jung-Hwan Park,Heo Jin-Seok,Jung Jaehoon,Lee Dongkeon,Kim Dae-Hyun,Dukha Park,Ki-Han Kim,Sang-Yun Kim,Jin-Sol Park,Hyunyoon Cho,Lim Sukhyun,Choi YeonKyu,Youngil Lim,Moon Daesik,Geuntae Park,Jang Jin-Hun,Kyung-Ho Lee,Isak Hwang,Kim Cheol,Younghoon Son,Kang Gil-Young,Park Kiwon,Lee Seungjun,Su-Yeon Doo,Shin Chang-Ho,Byongwook Na,Kwon Jisuk,Kim Kyung Ryun,Choi Hyein,Seouk-Kyu Choi,Chang Soobong,Wonil Bae,Kwon Hyuck-Joon,Young‐Soo Sohn,Bae Seung-Jun,Park Kwang‐Il,Jung-Bae Lee IEEE Conference Proceedings（2020）
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