Silicon Photonics Enabled Universal Cross-Scale Tensor Processing on Chip

Abstract In the rapidly evolving field of artificial intelligence, integrated photonic computing has emerged as a promising solution to address the growing demand for high-performance computing with increased speed and reduced energy consumption. This study presents a novel silicon photonic cross-scale tensor processing (SiP-CSTP) system on chip, designed to enhance the computing scale without increasing the hardware scale. By expanding the computing scale to accommodate the larger matrix processing scale, the SiP-CSTP system enables accelerated pooling, channel fusion, and matrix multiplication processes in convolutional neural networks. Notably, our architecture significantly reduces the number of operations required during pooling and channel fusion, distinguishing it from conventional computing systems. Experimental evaluations demonstrate the high-speed performance of the SiP-CSTP system, including a 14 Gbaud/s NRZ modulation rate for input tensors, a 6-bit accuracy for weight matrices, and an impressive total computing power of 0.252 TOPS, resulting computing power per unit as high as 0.06 TOPS /unit in a small hardware scale. Additionally, we conducted proof-of-concept application experiments on benchmark datasets, including the Modified National Institute of Standards and Technology (MNIST), Google quickdraw, and CIFAR-10. The results exhibited remarkable accuracies of 97.86%, 93.51%, and 70.22%, respectively, in deep image recognition and classification tasks. By enabling cross-scale operations in a universal tensor streaming processing system on a chip, this study opens new avenues for exploration and innovation at the intersection of silicon photonics, cross-scale computation, and artificial intelligence, shaping the future landscape of computing technologies.