A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector with Cascadable DTC Nonlinearity Compensation Algorithm
IEEE JOURNAL OF SOLID-STATE CIRCUITS（2024）
关键词
Charge pump phase-locked loop (CPPLL),fractional-N,frequency synthesizer,low jitter,phase noise,spur,time-amplifying phase-frequency detector (TAPFD)
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