Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling

S. Liao,L. Yang, T.K. Chiu,W.X. You, T.Y. Wu,K.F. Yang,W.Y. Woon,W.D. Ho, Z.C. Lin,H.Y. Hung,J.C. Huang,S.T. Huang, M.C. Tsai,C.L. Yu, S.H. Chen, K.K. Hu,C.C. Shih, Y.T. Chen, C.Y. Liu, H.Y. Lin, C.T. Chung, L. Su, C.Y. Chou, Y.T. Shen, C.M. Chang, Y.T. Lin,M.Y. Lin, W.C. Lin, B.H. Chen,C.S. Hou, F. Lai, X. Chen, J. Wu,C.K. Lin,Y.K. Cheng,H.T. Lin,Y.C. Ku,S.S. Lin, L.C. Lu,S.M. Jang,M. Cao

2023 International Electron Devices Meeting (IEDM)（2023）

Cited 3|Views30

Key words

Field-effect Transistors,Complementary Transistors,Gate Pitch,Complementary Field-effect Transistor,Current Ratio,Low Leakage,Architectural Practice,Vertical Stacking,Etching,Carrier Mobility,Inverter,Epitaxial Growth,Metal Work Function

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined