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Patterning Optimization for Single Mask Bit-Line-periphery and Storage-Node-landing-pad DRAM Layers Using 0.33NA EUV Lithography at the Resolution Limit

Van Tuong Pham, Jeonghoon Lee,Kaushik Sah, Ying-Lin Chen,Seonggil Heo,Soobin Hwang,Kenichi Miyaguchi,bappaditya Dey, Maria V. Chistiakova,Peter De Schepper,Philippe Bezard,Sara Paolillo,Danilo De Simone,Hyo Seon Suh,Victor M. Blanco Carballo

Advances in Patterning Materials and Processes XLI（2024）

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