High-Density Embedded 3-D Stackable Via RRAM in 16-Nm FinFET CMOS Logic Process
IEEE TRANSACTIONS ON ELECTRON DEVICES（2024）
Key words
Computer architecture,Resistance,FinFETs,Switches,Logic arrays,Layout,Stacking,3-D memory,CMOS logic process,embedded memory,nonvolatile memory (NVM),resistive random access memory (RRAM)
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