A 28nm 8928Kb/mm 2 -Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM.

Guodong Yin,Yiming Chen,Mingyen Lee,Xirui Du, Yue Ke,Wenjun Tang,Zhonghao Chen,Mufeng Zhou,Jinshan Yue,Huazhong Yang,Hongyang Jia,Yongpan Liu,Xueqing Li

IEEE Custom Integrated Circuits Conference（2024）

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关键词

Energy Efficiency,Density Data,Additional Weight,High Energy Efficiency,Reduction In Availability,Amount Of Movement,Transformer Layers,Reduction In Movement,Ultrahigh Density,Capacitor Size,Limited Memory Capacity,Sign Bit

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