A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays
IEEE Access（2024）
Key words
Codes,Redundancy,Error correction codes,Proposals,Random access memory,Transistors,Circuits,Radiation hardening (electronics),Error correcting codes,random multiple-bit upsets,radiation-hardened cells,soft errors,static RAM
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